The invention relates to electronic circuits, and in particular, to a multi-operating curve phase lock loop (PLL) and operating method thereof.
Current signal processing technologies are capable of processing the gigahertz frequency, and a PLL is the basis for a wide range of high frequency applications. By inputting a low frequency reference signal, a PLL generates a high frequency oscillation signal having a constant phase relationship with the reference signal.
FIG. 1 is a conventional PLL block diagram. A reference signal fref is input to the PLL and as a result, an oscillation signal fOSC is output. The reference signal fref is divided by R in the first divider 102, generating a corresponding divided signal f′ref. The phases or frequencies of the divided signal f′ref and a feedback signal fback are compared in a phase/frequency detector (PFD) 104, and the differences thereof generate a charging/sinking current. The loop filter 106 converts the current to an operating voltage VLF. A voltage controlled oscillator (VCO) 108 generates an oscillation signal fOSC based on the operating voltage VLF. The oscillation signal fOSC is further divided by N by the second divider 110, and the result is the feedback signal fback.
In order to provide oscillation signals of wider range frequencies, multi operating curves are developed on conventional PLLs. A desired oscillation frequency may be obtained by switching to an appropriate operating curve for an operation of the VCO.
FIG. 2 shows multi-operating curves of a conventional PLL. The VCO 108 comprises a plurality of operating curves each corresponding to an effective frequency range. Thus the PLL provides wide working range and improved flexibility. In the VCO 108, the operating voltage VLF is input and the oscillation signal fOSC is generated according to one of the operating curves VCO1 to VCOn. An effective method for selecting an appropriate VCO 108 for a desired oscillation signal fOSC is desirable.